The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Conventional egress queuing systems are typically configured so that a single packet can be enqueued in any particular queue in a given clock cycle. In the context of some networking or switching applications, an egress queuing system is shared by multiple packet processing cores of a network device. These multiple devices and cores together offer the ability to switch among a large number of ports. However, in such devices, multiple processing cores may need to simultaneously enqueue packets in a particular egress queue.
Some attempts have been made to design egress queuing systems that allow multiple packets to be enqueued in a single egress queue in a given clock cycle. For example, egress queues can be stored in a memory device that runs on a faster clock relative to a clock used by packet processing cores, allowing multiple packets to be written to a same queue in a single clock cycle of the packet processing cores. Additionally or alternatively, a width of a memory device can be increased to allow more packets to be written to a same queue in a single clock cycle of the memory device. Such methods, however, are limited with respect to the maximum number of packets that can be written to a same queue in a given clock cycle. Further, such methods are not readily scalable to support larger numbers of egress queues and/or larger numbers of packet processing cores in a network device.